R/W

S

Slave Address

(7 bits)

'0' A

A

Control Register Add.

(8 bits)

From Slave to Master

From Master to Slave

Slave Address

(7 bits)

A

Sr

'1'

R/W

Data transferred, byte +

Ack/NAck

Register Data

(8 bits)

P

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

NA - ACKNOWLEDGE (SDA High)

Sr - REPEATED START CONDITION

Direction of the transfer

will change at this point

NA

A/

LP8725

www.ti.com

SNVS618G – DECEMBER 2009 – REVISED MAY 2013

Figure 19. Register Read Format

Layout Guidelines

As for all DC-DC buck regulators board layout is very important to ensure best performance.

The 4.7 µF input capacitors should be placed first, as near to VINB1/2 pin and GNDB1/2 as possible. VINB1/2

are the voltage rails for the high-side power FETs. GNDB1/2 are the return paths for the low-side power FETs.

The Input capacitors should have their associated pads very near the pins that they will decouple. These

capacitors are important in sourcing charge during switching events. In this device we have the two buck inputs

side by side but we recommend that separate traces are taken to each device pin to ensure this proper

decoupling. This can be seen in the example layout shown in the layout scheme below.

The 4.7 µF output capacitors should be the next components to be placed in conjunction with the inductor. The

switch node should be kept as small as possible but otherwise the inductor placement is least sensitive to layout

variation. Best performance of the LP8725 will be realized by maintaining tight physical coupling of the grounds

of the input capacitor, output capacitor and GND pin for each switcher. The inductor should be placed in a way

that best allows the switching node, output node, and track to the load circuit to be routed easily.

The grounding is very important and any additional resistance/inductance should be minimized. A ground

polygon and/or plane should be used to tie all capacitor grounds together and directly to the buck GNDs. See the

layout scheme below as an example.

Finally, the feedback nets should be routed, where possible route this away from any switching nodes and tie

into the output node of the regulator. The FB lines should closely match the GND routing to reduce the inductive

loop of this pair. The FB and GND lines make up a high-side and low-side sense connection to maintain the

accuracy of the switcher outputs. If the FB line should cross the switching trace make this as close to

perpendicular as possible.

Low impedance power connections should be maintained for all of these connections. Care should also be given

to the ground routing for input lines and output lines to minimize inductive loops, normally this should be taken

care of by suitable ground planes.

As this is a dual buck device there are a number of aspects to be aware of. The switchers are almost a complete

mirror image of one another on the part which leads to the possibility of symmetrical placement and layout about

the part. Symmetrical layout will give best matching between the two buck devices. However we recommend that

the inputs are kept separate into the device. There are some compromises that have to be considered. In the

case of our example we have used vias to route the VINB12 and VINB2 to allow the close placement of the input

capacitors. The switch node must also be routed via layer2 on the board. Here we have placed a number of vias

to reduce any additional impedance.

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