TNETX3150GGP datasheet(21/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

receive arbitration

Receive arbitration biases the prioritization of the arbitration for received frames over transmitted frames. This

utilizes the TNETX3150/TNETX3150A buffering capability during heavy traffic loading, while increasing

transmission latency of the TNETX3150/TNETX3150A. Receive arbitration is selected by setting the RXARB

bit (bit 5) in the serial input/output (SIO) register.

The normal arbitration scheme is extended to bias the receive priority and active transmissions over inactive

transmissions. The queue manager services buffer transfer requests between the port FIFOs and DRAM.

Receive requests and ongoing transmit requests take priority over transmissions that have not started (inactive

transmissions). If there are spare DRAM accesses available, an inactive transmit request is promoted to an

active transmit request. If there are no spare DRAM accesses, the transmit requests are arbitrated and all

ongoing transmissions are allowed to finish, with no new transmission started until the receive requests are

exhausted.

Port 00, when operated in uplink mode, is always assigned the transmit inactive priority. Even when granted

an active TX slot, one buffer is transferred (following the initial two buffers accrued before a frame start) before

the port renegotiates another TX active slot. Thus, port 00 TX in uplink mode has the lowest possible priority,

reducing the probability of frame loss through oversubscribed bandwidth, while increasing frame latency and

buffering requirements. When operating in this mode, external hardware must be provided to reconstruct the

frame due to port 00 uplink operation.

data transmission

Figure 4 shows a simplified 10-/100-/200-Mbit/s transmit block diagram.

Buffer

CRC

Flag

Information

Shifter

Buffer

Bit

FIFO Control

and Statistics

Information

Data

MUX

10-/100-

Mbit/s

Converter

Rate

Select

Data Output

Duplex

Nibble

Input From

FIFO

Flags Input From FIFO

TX Frame

TX FIFO

Control

Signal

Figure 4. 10-/100-/200-Mbits Transmit Block Diagram

serialization

Data entering from the FIFO as a 64-bit word is serialized for transmission at the transmit clock rate. This also

requires the data to be synchronized to the transmit clock rate from the TNETX3150/TNETX3150A internal

clock. The CRC block is used only to check that the frame still has a valid CRC. It is not used to recalculate a

new CRC for the frame. If the CRC does not match, the frame contents were corrupted through the switch and

are counted in the TX data-error counter.

backoff

The TNETX3150/TNETX3150A implements the IEEE Std 802.3 binary exponential backoff algorithm.

TNETX3150GGP 数据表(PDF) 21 Page - Texas Instruments

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