TNETX3150GGP datasheet(69/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

buffer allocation (continued)

The total number of buffers available to the TNETX3150/TNETX3150A is determined by the size of the external

memory. The RSIZE (RAM size) field of the RAM size register is loaded from the EEPROM or from the DIO

interface with the appropriate system RAM code. The TNETX3150/TNETX3150A uses this size information to

modify the DRAM addressing limit when initializing the buffer data structures. The DRAM is initialized to contain

a single list of data buffers (free buffer queue) available to all queues. The least-significant byte of the DRAM

address is incremented in steps of 17 (decimal). During initialization, the normal TNETX3150/TNETX3150A

operation is disabled. Once the buffer structure has been created in the DRAM, no further use is made of the

sizing information.

The queue size for the transmit queues can be increased by adding a 2’s complement number (representing

the number of buffers that need to be added to the queue) to the transmit queue-length field. Reducing the

number of buffers allocated to the ports is done in the same way by adding a negative-length field. The length

is updated after the transmission of a buffer. The update bit is cleared after the update occurs.

There is no checking between the number of free buffers physically available in memory and the number of

buffers allocated to each queue. It is possible to oversubscribe the memory between the queues. If a frame is

being buffered when the buffer ceiling is reached, all buffers constituting that incomplete queue of buffers are

purged and replaced on the free buffer stack or queue. Thus, during memory limitation, large frames are

inherently filtered in favor of smaller frames. When all buffers are subscribed and none are available for use,

the TNETX3150/TNETX3150A accepts no new frames, but waits for buffers to be freed before continuing.

QMU – DRAM controller

Within the queue manager, the DRAM control block provides the interface to the external DRAM buffer memory.

The interface control signals required are produced by the QMU, which controls the data transfer with the

DRAM.

The interface relies on the use of EDO DRAM to minimize the access time, while maintaining RAM bandwidth.

The TNETX3150/TNETX3150A requires EDO DRAM operating at 60 ns. The use of EDO DRAM permits the

high data-transfer rates required by the TNETX3150/TNETX3150A.

The DRAM is accessed in a number of ways:

Single access – used during initialization and forward pointer writes. This is the slowest-access method and

transfers a single 36-bit word. Each access takes seven 20-ns clock cycles (see Figures 2 and 4).

Page-mode burst access – used for fast data transfer of one 64-byte buffer from the FIFO RAM to the

DRAMs. The locations used are located within the DRAMs page boundary, permitting fast burst accesses

to be made. Each successive burst access requires only two clock cycles after the initial row address has

been loaded (see Figure 9).

Dynamic memories must be refreshed periodically to prevent data loss. Each row refresh cycle requires a

minimum of seven clock cycles and must be performed such that the whole device is refreshed every 16 ms.

A normal read or write operation refreshes the whole row being accessed (see Figure 5).

The external DRAM data bus is 36 bits wide. Buffer data is accessed over two memory cycles from the DRAM

before it is concatenated into an 8-byte data word and one byte of flag data. The format of the 36-bit data word

used is shown in Figure 28.

DRAM DATA BUS FORMAT

FLAG DATA

32-BIT DATA

Figure 28. DRAM Data Bus Format

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