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TNETX3150GGP 数据表(PDF) 90 Page - Texas Instruments |
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TNETX3150GGP 数据表(HTML) 90 Page - Texas Instruments |
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90 / 113 page  TNETX3150/TNETX3150A ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997 90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (see Notes 8 and 9 and Figure 36) DRAM CAS-before-RAS (CBR) refresh cycle NO. MIN NOM MAX UNIT 1 tc(OSCIN) Cycle time, OSCIN clock 20 ns 2 tw(OSCINH) Pulse duration, OSCIN high 8 ns 3 tw(OSCINL) Pulse duration, OSCIN low 8 ns Frequency drift, OSCIN clock ±50 ppm NOTES: 8. All DRAM output signals are synchronous to the DREF clock. 9. The TNETX3150/TNETX3150A produces a refresh request at a fixed rate of once every 10.22 µs. If a block transfer is underway, the refresh is deferred. operating characteristics over recommended operating conditions (see Notes 8 and 9 and Figure 36) DRAM CAS-before-RAS (CBR) refresh cycle (with DREF clock) NO PARAMETER TNETX3150 TNETX3150A UNIT NO. PARAMETER MIN TYP MAX MIN TYP MAX UNIT 4 tc(DREF) Cycle time, DREF clock 20 20 ns 5 td(DCAS) Delay time, from DREF ↑ to DCAS transition –4 4 –4 3 ns 6 td(DRAS) Delay time, from DREF ↑ to DRAS transition -4 5 -4 3 ns 7 td(DOE) Delay time, from DREF ↑ to DOE transition –4 5 –4 3 ns 8 td(DWE) Delay time, from DREF ↑ to DWE transition –4 4 –4 3 ns NOTES: 8. All DRAM output signals are synchronous to the DREF clock. 9. The TNETX3150/TNETX3150A produces a refresh request at a fixed rate of once every 10.22 µs. If a block transfer is underway, the refresh is deferred. operating characteristics over recommended operating conditions (see Notes 9 and 10 and Figure 36) DRAM CAS-before-RAS (CBR) refresh cycle (with OSCIN clock) NO PARAMETER TNETX3150 TNETX3150A UNIT NO. PARAMETER MIN MAX MIN MAX UNIT 9 td(DCAS) Delay time, from OSCIN ↑ to DCAS transition 3 15 3 15 ns 10 td(DRAS) Delay time, from OSCIN ↑ to DRAS transition 3 15 3 15 ns 11 td(DOE) Delay time, from OSCIN ↑ to DOE transition 3 15 3 15 ns 12 td(DWE) Delay time, from OSCIN ↑ to DWE transition 3 15 3 15 ns NOTES: 9. The TNETX3150/TNETX3150A produces a refresh request at a fixed rate of once every 10.22 µs. If a block transfer is underway, the refresh is deferred. 10. All DRAM output signals are synchronous to the OSCIN clock. Figure 15 shows a single DRAM write (TNETX3150/TNETX3150A forward pointer update). |
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