TNETX3150GGP datasheet(49/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

RAM size register at 0x00C2

BIT

MTEST

Reserved

TAGOFF

RSIZE

Initial Values After Reset

BIT

NAME

FUNCTION

MTEST

Test access bit. MTEST = 1 before DIO accesses are made to the DIO test registers (address range 0xDC–0xFF).

MTEST = 0 when the EEPROM is used to initialize registers 0x00–0xC3. The default value after reset is 0. MTEST

allows access to the DIO registers to enable frame-wrap test modes.

6–5

Reserved

TAGOFF

Post-frame tag disable bit. TAGOFF disables the requirement for post-frame tagging when operating in 200-Mbit/s

wide uplink mode. In this mode (TAGOFF = 1), the TNETX3150/TNETX3150A uses either the EAM interface or

the internal single-address lookup registers to route frames received on the uplink. This permits two

TNETX3150/TNETX3150A devices to be cascaded.

RSIZE

RAM size select. This field indicates the size of the external DRAM and, therefore, the number of 64-byte data

buffers available.† This field is used by the TNETX3150/TNETX3150A to determine how many buffers to initialize.

The code values are:

3–0

RSIZE

BIT

CODE

NUMBER OF

VALUES

BUFFERS

0000–0011

Reserved

—

0100

× 36

240

0101

× 36

480

3–0

RSIZE

0110

16K

× 36

961

0111

32K

× 36

1922

1000

64K

× 36

3845

1001

128K

× 36

7690

1010

256K

× 36

15,380

1011

512K

× 36

30,720

RSIZE

1100

× 36

61,440

3–0

RSIZE

1101

× 36

122,880

1110

× 36

245,760

1111

Reserved

—

† Buffers are 76.5 bytes long (four bytes of forward pointer). Fifteen 76.5-byte buffers are allocated per 1K-byte page. The first word of every 1K-byte

page is not used. Buffers never straddle page boundaries.

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