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TNETX3150GGP 数据表(PDF) 86 Page - Texas Instruments |
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TNETX3150GGP 数据表(HTML) 86 Page - Texas Instruments |
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86 / 113 page  TNETX3150/TNETX3150A ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997 86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (see Note 4 and Figure 34) DRAM read cycle NO TNETX3150 TNETX3150A UNIT NO. MIN NOM MAX MIN NOM MAX UNIT 1 tc(OSCIN) Cycle time, OSCIN clock 20 20 ns 2 tw(OSCINH) Pulse duration, OSCIN high 8 8 ns 3 tw(OSCINL) Pulse duration, OSCIN low 8 8 ns Frequency drift, OSCIN clock ±50 ±50 ppm NOTE 4: All DRAM output signals are synchronous to the DREF clock. Figure 14 shows a single DRAM read (TNETX3150/TNETX3150A forward pointer update). operating characteristics over recommended operating conditions (see Note 4 and Figure 34) DRAM read cycle NO PARAMETER TNETX3150 TNETX3150A UNIT NO. PARAMETER MIN TYP MAX MIN TYP MAX UNIT 4 tc(DREF) Cycle time, DREF clock 20 20 ns 5 td(DD)1 Delay time, from DREF ↑ to DD35–DD0 valid 24 25 ns 6 td(DD)2 Delay time, from DREF ↑ to DD35–DD0 invalid 3 0 ns 7 td(DA) Delay time, from DREF ↑ to DA7–DA0 valid/invalid –4 3 –4 3 ns 7 td(DX) Delay time, from DREF ↑ to DX2–DX0 valid/invalid –4 3 –4 3 ns 8 td(DRAS) Delay time, from DREF ↑ to DRAS transition –4 5 –4 3 ns 9 td(DWE) Delay time, from DREF ↑ to DWE transition –4 4 –4 3 ns 10 td(DCAS) Delay time, from DREF ↑ to DCAS transition –4 4 –4 3 ns 11 td(DOE) Delay time, from DREF ↑ to DOE transition –4 5 –4 3 ns NOTE 4: All DRAM output signals are synchronous to the DREF clock. Figure 14 shows a single DRAM read (TNETX3150/TNETX3150A forward pointer update). operating characteristics over recommended operating conditions (see Note 5 and Figure 34) DRAM read cycle NO PARAMETER TNETX3150 TNETX3150A UNIT NO. PARAMETER MIN MAX MIN MAX UNIT 12 td(DA) Delay time, from OSCIN ↑ to DA7–DA0 valid/invalid 3 15 3 15 ns 12 td(DX) Delay time, from OSCIN ↑ to DX2–DX0 valid/invalid 3 15 3 15 ns 13 td(DRAS) Delay time, from OSCIN ↑ to DRAS transition 3 15 3 15 ns 14 td(DWE) Delay time, from OSCIN ↑ to DWE transition 3 15 3 15 ns 15 td(DCAS) Delay time, from OSCIN ↑ to DCAS transition 3 15 3 15 ns 16 td(DOE) Delay time, from OSCIN ↑ to DOE transition 3 15 3 15 ns NOTE 5: All DRAM output signals are synchronous to the OSCIN clock. Figure 14 shows a single DRAM read (TNETX3150/TNETX3150A forward pointer update). |
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