PC87591L datasheet(35/437 Pages) NSC

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1.0 Introduction (Continued)

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Either byte-wide or word-wide transactions to any address within the memory address space may be used to access memory

devices.

Only byte-wide transactions may be used to access byte-wide registers, and only word-wide transactions may be used to

access word-wide registers. Attempts to read a write-only register or write to a read-only register cause unpredictable re-

sults.

Zeros must be written to reserved bits unless stated otherwise. Reading reserved bits returns an undefined value. When

modifying a register with reserved bits, the data read from reserved a bit can be written back to it.

Accessing Base Memory

In the PC87591E and PC87591S the Base memory is the main storage for code and data. When Shared BIOS is enabled,

the Base memory may also be used for storing BIOS code and data. Figure 6 on page 35 illustrates how on-chip and off-

chip Base Memory are mapped to the PC87591E and PC87591S address space.

The Base Memory is divided into two zones:

●

Fast Zone - for addresses with Base Memory in the range of 00 0000 to 01 FFFF. The access time to this zone is

controlled by the BIU Zone 1 conﬁguration registers.

●

Slow Zone - for addresses with Base Memory in the range of 02 0000 to 0F FFFF. The access time to this zone is

controlled by the BIU Zone 2 conﬁguration registers.

In the PC87591L, the base memory is used for storing code and data required for basic boot operations. The rest of the code

and data are stored in the Expansion Memory shared by the core firmware and host BIOS. Figure 7 on page 36 illustrates

how on-chip and off-chip Base Memory are mapped to the PC87591L address space.

IRE and OBD Environments - On-Chip Base Memory. In IRE and OBD environments, the on-chip flash (ROM) is used as

Base memory. Note that the size of the available memory may differ among members of PC87591x family (see Tables 1 to

3). The access time to it is controlled by BIU Zones 1 and 2. To allow cycle-by-cycle compatibility with DEV environment,

both zones should be programed in the same way for all environments. Thus to maximize on-chip flash (ROM) performance,

configure BIU Zones 1 and 2, as described in Section 4.1.11 on page 86 and Section 4.16 on page 218, with minimal access

time supported at the frequency in use, as defined in “Flash Read, Write and Erase Time” on page 222.

Off-Chip Base Memory. In DEV environment (when on-chip flash is disabled), the code and constant data are stored in off-

chip Base Memory. In the PC87591E and PC87591S, this off-chip Base Memory has 1016 Kbytes of address space

(00 000016 to 00 DFFF16 and 01 000016 to 0F FFFF16). In the PC87591L, the size of the off-chip Base Memory is 4 Kbytes.

To ensure that the code fits into the on-chip flash in IRE and OBD environments later on, both the code and constant data

should fit within the defined flash size, for the selected member of the PC87591x family.

56 K

64 K

Off-Chip Base Memory

On-Chip Base Memory

Figure 6. Base Memory Address Mapping - PC87591E and PC87591S

56 K

128K

Core Address Map

00 0000

02 0000

Zone 2

Access Time

01 FFFF

0F FFFF

Control

Zone 1

Access Time

Control

2 M

1 M

PC87591S

Flash Size

PC87591E

Flash Size

PC87591L 数据表(PDF) 35 Page - National Semiconductor (TI)

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