PC87591L datasheet(95/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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ETC (Enable Interrupt on Terminal Count). Enables a level interrupt, when TC bit is set.

0: Interrupt masked

1: Interrupt enabled

EOVR (Enable Interrupt on OVR). Enables a level interrupt, when OVR bit is set.

0: Interrupt masked

1: Interrupt enabled

TCS (Transfer Cycle Size). Speciﬁes the number of bytes transferred in each DMA transfer cycle. In Direct

(Fly-By) mode, undeﬁned results occur if TCS is not equal to the addressed memory bus width.

0: Byte wide transfer

1: Word-wide (16-bit) transfer

IND (Direct/Indirect Transfer). Transfer Type.

0: Direct (Fly-By)

1: Indirect (Memory-to-Memory)

DIR (Transfer Direction). Speciﬁes the direction of the transfer relative to Device A.

0: Device A (pointed to by ADCAn) is the source. In Fly-By mode, a read transaction is initialized.

1: Device A (pointed to by ADCAn) is the destination. In Fly-By mode, a write transaction is initialized.

6OT (Operation Type).

0: Single-Buffer mode or Double-Buffer mode enabled

1: Auto-Initialize mode enabled

BPC (Bus Policy Control). Intermittent (cycle stealing) or continuous (burst).

0: Intermittent operation. DMAC channel n relinquishes the bus after each transaction even if the request is still

asserted.

1: Continous operation. DMAC channel n uses the bus continuously as long as the request is asserted. This mode

can only be used for SW DMA requests (i.e., when SWRQ is set). On HW DMA requests, BPC must be set to 0.

SWRQ (Software DMA Request).

0: Software DMA request is inactive

1: Software DMA request is active

ADA (Device A Address Control). Enables Update of Device A Address.

0: ADCAn address unchanged

1: ADCAn address incremented or decremented, according to INCA field

11-10 INCA (Increment/Decrement ADCAn).

Bits

11 10 Description

0 0:

Increment ADCAn register by 1

0 1:

Increment ADCAn register by 2

1 0:

Decrement ADCAn register by 1

1 1:

Decrement ADCAn register by 2

ADB (Device B Address Control). Enables Update of Device B Address.

0: ADCBn address unchanged

1: ADCBn address incremented or decremented, according to INCB field

14-13 INCB (Increment/Decrement ADCBn).

Bits

14 13 Description

0 0: Increment ADCBn register by 1

0 1: Increment ADCBn register by 2

1 0: Decrement ADCBn register by 1

1 1: Decrement ADCBn register by 2

Reserved.

Bit

Description

PC87591L 数据表(PDF) 95 Page - National Semiconductor (TI)

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