PC87591L datasheet(72/437 Pages) NSC

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4.0 Embedded Controller Modules (Continued)

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Burst Read Cycles A read bus cycle consisting of the basic bus cycle plus additional clock cycles called “burst bus cycles”.

The burst bus cycles occur if the bus is burstable (BRE in SZCFGn register is 1), the configured bus width is eight bits and

the core attempts to read a word. When the bus is not burstable (BRE in SZCFGn register is 0), the BIU issues two separate

read bus cycles. Write bus cycles are never burstable, and the BIU always issues two separate write bus cycles.

Control Signals

The write bus cycles use byte write qualifiers on WR0-1 pins:

●

They access an 8-bit wide memory on D0-7 data lines.

One byte is accessed on basic bus cycles. Only the WR0 pin is used as the byte write qualiﬁer.

●

They access a 16-bit wide memory on D0-15 data lines.

Either one or two bytes are accessed on basic bus cycles. The WR0 pin is used as an even byte (D0-7) write qualiﬁer

and WR1 pin is used as an odd byte (D8-15) write qualiﬁer.

4.1.4

Early Write Bus Cycle

If EWR in BCFG register is 1, the BIU uses early write bus cycles. This allows removal of the RD signal from the memory

device interface. The basic early write bus cycle takes three clock cycles.

The cycle starts at T1; at this point, the data bus is in TRI-STATE, the address is placed on the address bus and RD is in-

active. indicating that this is a write bus cycle. Then, WR0-1 are activated.

At the first TIW or T2 (when there are no TIW cycles), the data is placed on the data bus and the SELn (or SELIO) is acti-

vated. The bus transaction is terminated at T3; at this point, SELn (or SELIO) becomes inactive. Then WR0-1 become in-

active and the data bus is put in TRI-STATE. The address remains valid until T3 is complete.

Thold clock cycles may follow T3, according to HOLD in SZCFGn or IOCFG registers (may be 0). The address and data re-

main valid until the end of the last Thold cycle. The data is put in TRI-STATE in the clock cycle after the last Thold or T3 (if no

Thold cycle is configured); see Figures 12, 13 and 14.

If a read bus cycle immediately follows an Early Write bus cycle, an idle cycle is added between the two.

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