PC87591L datasheet(96/437 Pages) NSC

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Embedded Controller Modules (Continued)

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DMA Status Register (DMASTATn)

A byte-wide, read with write 1 to clear register that holds the status information for the DMAC channel. On reset, the imple-

mented bits are initialized to 0. The reserved bits always return zero when read.

The format of the DMASTATn register is shown below.

Location: Channel 0 - 00 FA1E16

Channel 1 - 00 FA3E16

Channel 2 - 00 FA5E16

Channel 3 - 00 FA7E16

Type: R/W1C

Bit

76543210

Name

Reserved

VLD

CHAC

OVR

Reset

00000000

Bit

Description

TC1 (Terminal Count). When set to 1, indicates that the transfer was completed by a terminal count condition

(BLTCn register reached 0).

1. The VLD, OVR and TC bits are sticky (once set by the occurrence of the speciﬁc condition, they remain set until

explicitly cleared by software). These bits can be cleared individually by writing a value into the DMASTATn reg-

ister with the bit positions to be cleared set to 1; writing 0 to these bits has no effect.

OVR1 (Channel Overrun).

• In double buffered operation (OT bit in DMACNTLn register is 0):

OVR is set to 1 when the present transfer is completed (BLTC = 0), but the parameters for the next transfer

(address and block length) are not valid.

• In auto initialize operation: (OT bit in DMACNTLn register is 1)

OVR is set to 1 when the present transfer is completed (BLTC = 0), but TC bit is still set to 1 (e.g., the software

did not serve the last interrupt).

• In single buffer operation:

This bit is ignored.

CHAC (Channel Active). Continuously reﬂects the active or inactive status of the channel and is therefore read

only. Data written to CHAC bit is ignored.

0: Indicates that the channel is inactive

1: Indicates that the channel is active (CHEN bit in DMACNTLn register is 1 and BLTC > 0)

VLD1 (Transfer Parameters Valid). Speciﬁes whether the transfer parameters for the next block to be

transferred are valid.

Writing to the BLTRn register sets this bit to 1.

It is cleared to 0 in the following cases:

• The present transfer is completed, and the ADRAn, ADRBn (Indirect mode only) and BLTR registers are copied

to the ADCAn, ADCBn (Indirect mode only) and BLTCn registers, respectively.

• Writing 1 to VLD bit; (writing zero has no effect).

7-4

Reserved.

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