PC87591L datasheet(80/437 Pages) NSC

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4.0 Embedded Controller Modules (Continued)

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The fast read bus cycle cannot be extended by adding wait cycles (WAIT field in SZCFGn register is ignored during this bus

cycle). Additionally, hold cycles cannot be added (HOLD field in SZCFGn register is also ignored). When a write bus cycle

immediately precedes, in sequence, a fast read bus cycle, an idle clock cycle is forced between the two; see Figure 23.

Note that when the core attempts to access more bytes than the configured bus width (i.e., a word), the transaction is broken

up into “basic” (T1-2) bus cycles.

4.1.8

I/O Expansion Bus Cycles

The I/O expansion bus cycles support the implementation of on-chip I/O port functionality (when the pins of the on-chip I/O

ports are used to support DEV environments) and/or additional ports, using off-chip external logic.

I/O expansion bus cycles access the off-chip I/O device using the following signals:

●

SELIO.

●

Address lines A0-7.

●

The RD and WR0-1 signals may be used.

The design minimizes the off-chip logic required to implement the I/O ports. It is costly to implement a port with pins individ-

ually configured for input or output. Implementing ports for input only or output only reduces expenses.

I/O expansion bus cycle is not generated during an access to a port register if one of the following conditions occurs:

●

A port pin is available on-chip.

●

All port pins are inputs and the port is being written.

CLK

A0-19

SELx

SELy

WR0-1

D0-15

Fast

Late Write

Fast

TIdle

T1-2

Read

TIdle

Out

BST0-2

≠ y)

≠ x)

Idle

Cycle

Figure 23. Fast Read Bus Cycle

Bus State

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