PC87591L datasheet(97/437 Pages) NSC

97 / 437 page

Embedded Controller Modules (Continued)

Revision 1.07

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4.2.9

Usage Hints

●

Do not write to ADCAn, ADCBn or BLTCn and do not change the value of TCS, IND, DIR, OT, ADA, INCA, ADB and

INCB ﬁelds of DMACNTLn register while the associated channel is active (CHAC bit in DMASTATn register is 1).

When initializing these registers, write to BLTCn register last, since writing to BLTCn register activates the channel

immediately (if CHEN bit in DMACNTLn register is set to 1).

●

The ADRAn, ADRBn and BLTRn registers store transfer parameters (source address, destination address and block

length) for the next data block to be transferred, for either Auto-Initialize or Double-Buffer modes of operation. When

initializing these registers, write the BLTRn register last, since this validates the next block’s parameters (VLD bit in

DMASTATn register is set to 1).

●

The TCS bit in DMACNTLn register is programed according to the bus width of the devices. It determines how many

bytes are transferred in each DMA bus cycle.

●

The DMAC does not support non-aligned transfers. The values written to ADCAn, ADRAn, ADCBn and ADRBn must

be multiples of the Transfer Cycle Size (as deﬁned by TCS bit in DMACNTLn register).

PC87591L 数据表(PDF) 97 Page - National Semiconductor (TI)