PC87591L datasheet(6/437 Pages) NSC

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Revision 1.07

Table of Contents

Embedded Controller System Features ................................................................. 2

Host Controlled Functions Features ...................................................................... 3

Clocking, Supply and Package Information ........................................................... 4

Revision Record .................................................................................................... 5

1.0

Introduction

1.1

DOCUMENT ORGANIZATION .................................................................................................. 23

1.2

GENERAL DESCRIPTION ........................................................................................................ 23

1.2.1

System Connections .................................................................................................... 23

1.2.2

Power Management .................................................................................................... 23

1.2.3

Operating Environments .............................................................................................. 25

1.3

INTERNAL ARCHITECTURE .................................................................................................... 25

1.3.1

Processing Unit ........................................................................................................... 26

1.3.2

Bus Interface Unit and Memory Controller (BIU) ......................................................... 26

1.3.3

On-Chip Memory ......................................................................................................... 26

1.3.4

Peripherals .................................................................................................................. 27

1.3.5

Host-Controller Interface Modules ............................................................................... 28

1.3.6

Host-Controlled SuperI/O Modules and Host Interface ............................................... 29

1.4

OPERATING ENVIRONMENTS ................................................................................................ 29

1.4.1

IRE Environment ......................................................................................................... 29

1.4.2

OBD Environment ........................................................................................................ 30

1.4.3

DEV Environment ........................................................................................................ 30

1.4.4

PROG Environment ..................................................................................................... 30

1.5

MEMORY MAP .......................................................................................................................... 30

1.5.1

Core Address Domain Memory Map ........................................................................... 33

Accessing Base Memory ..................................................................................... 35

Accessing Expansion Memory ............................................................................. 36

Accessing I/O Expansion Space .......................................................................... 37

1.5.2

Host Address Domain Memory Map ............................................................................ 38

1.5.3

Core Access to Host Controlled Peripherals ............................................................... 38

2.0

Signal/Pin Description and Configuration

2.1

CONNECTION DIAGRAMS ...................................................................................................... 39

2.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 41

2.2.1

ACCESS.bus (ACB1 and ACB2) Interface .................................................................. 42

2.2.2

Analog Interface .......................................................................................................... 42

2.2.3

Clocks .......................................................................................................................... 42

2.2.4

Core Bus Interface Unit (BIU) ...................................................................................... 43

2.2.5

Development System Support ..................................................................................... 44

2.2.6

General-Purpose I/O (GPIO) and Internal Keyboard Scan ......................................... 45

2.2.7

Host Interface .............................................................................................................. 48

2.2.8

Interrupt and Wake-Up Inputs (ICU and MIWU) .......................................................... 49

2.2.9

Power and Ground ...................................................................................................... 49

2.2.10

PS/2 Interface .............................................................................................................. 50

2.2.11

Strap Configuration ...................................................................................................... 50

PC87591L 数据表(PDF) 6 Page - National Semiconductor (TI)

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