Copyright © 2014 Future Technology Devices International Limited

44

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Clearance No.: FTDI#

312

Appendix A – References

Useful Application Notes

http://www.ftdichip.com/Documents/AppNotes/AN_167_FT1248_Parallel_Serial_Interface_Basics.pdf

http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_100_USB_VID-PID_Guidelines.pdf

http://www.ftdichip.com/Support/Documents/AppNotes/AN_175_Battery%20Charging%20Over%20USB

%20with%20FTEX%20Devices.pdf

http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip

Appendix B - List of Figures and Tables

List of Figures

Figure 2-1 FT121 Block Diagram.....................................................................................................3

Figure 3-1 TSSOP-16 package schematic symbol ..............................................................................6

Figure 3-2 QFN-16 package schematic symbol..................................................................................6

Figure 4-1 SPI access.................................................................................................................. 11

Figure 4-2 4-wire write operation.................................................................................................. 11

Figure 4-3 4-wire read operation .................................................................................................. 12

Figure 4-4 3-wire write operation.................................................................................................. 12

Figure 4-5 3-wire read operation .................................................................................................. 12

Figure 7-1 FT121 bus powered application ..................................................................................... 33

Figure 7-2 FT121 self powered application ..................................................................................... 33

Figure 8-1 SPI slave timing .......................................................................................................... 37

Figure 9-1 TSSOP-16 Package Dimensions ..................................................................................... 38

Figure 9-2 TSSOP-16 Package Markings ........................................................................................ 39

Figure 9-3 QFN-16 Package Dimensions ........................................................................................ 40

Figure 9-4 QFN-16 Package Markings ............................................................................................ 41

Figure 9-5 FT121 Solder Reflow Profile .......................................................................................... 41

List of Tables

Table 3.1 FT121 Pin Description......................................................................................................7

Table 4.1 Interrupt modes ........................................................................................................... 10

Table 5.1 Endpoint configuration for EP0 and EP1 ........................................................................... 14

Table 5.2 Endpoint configuration for EP2 ....................................................................................... 14

Table 5.3 Example buffer configuration.......................................................................................... 15

Table 5.4 Endpoint Maximum Packet Size ...................................................................................... 16

Table 6.1 FT121 default command set ........................................................................................... 18

Table 6.2 enhanced command set................................................................................................. 22

Table 6.3 Address Enable Register ................................................................................................ 22

Table 6.4 Endpoint Enable Register ............................................................................................... 22

Table 6.5 Configuration Register (Byte 1) ...................................................................................... 23

Table 6.6 Configuration Register (Byte 2) ...................................................................................... 23

Table 6.7 Interrupt Configuration Register ..................................................................................... 24