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STM32F303VC 数据表(PDF) 96 Page - STMicroelectronics

部件名 STM32F303VC
功能描述  ARM®-based Cortex®-M4 32b MCUFPU, up to 256KB Flash 48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V
PDF  148 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F303VC 数据表(HTML) 96 Page - STMicroelectronics

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Electrical characteristics
STM32F303xB STM32F303xC
96/148
DocID023353 Rev 13
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 24.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 63. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode, SPI1
2.7<VDD<3.6
--
24
MHz
Slave mode, SPI1
2.7<VDD<3.6
24
Master mode, SPI1/2/3
2<VDD<3.6
18
Slave mode, SPI1/2/3
2<VDD<3.6
18
DuCy(SCK) Duty cycle of SPI clock frequency
Slave mode
30
50
70
%
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
ns
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
tsu(MI)
Data input setup time
Master mode
5.5
-
-
tsu(SI)
Slave mode
6.5
-
-
th(MI)
Data input hold time
Master mode
5
-
-
th(SI)
Slave mode
5
-
-
ta(SO)
Data output access time
Slave mode
0
-
4*Tpclk
tdis(SO)
Data output disable time
Slave mode
0
-
24
tv(SO)
Data output valid time
Slave mode
-
12
27
Slave mode, SPI1
2.7<VDD<3.6V
-12
18
tv(MO)
Master mode
-
1.5
3
th(SO)
Data output hold time
Slave mode
11
-
-
th(MO)
Master mode
0
-
-
1. Guaranteed by characterization results.



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