STM32F303VC datasheet(16/148 Pages) STMICROELECTRONICS

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Functional overview

STM32F303xB STM32F303xC

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DocID023353 Rev 13

3.7.4

Low-power modes

The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best

compromise between low-power consumption, short startup time and available wakeup

sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC

alarm, COMPx, I2Cx or U(S)ARTx.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin or an RTC alarm occurs.

Note:

The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DAC1

Conversion triggers

DMA

Memory to memory transfer trigger

Compx

Comparator output blanking

COMPx

TIMx

Timer input: OCREF_CLR input, input capture

ADCx

TIMx

Timer triggered by analog watchdog

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