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STM32F303VC 数据表(PDF) 99 Page - STMicroelectronics |
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STM32F303VC 数据表(HTML) 99 Page - STMicroelectronics |
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99 / 148 page ![]() DocID023353 Rev 13 99/148 STM32F303xB STM32F303xC Electrical characteristics 124 Table 64. I2S characteristics(1) 1. Guaranteed by characterization results. Symbol Parameter Conditions Min Max Unit fCK 1/tc(CK) I2S clock frequency Master data: 16 bits, audio freq=48 kHz 1.496 1.503 MHz Slave 0 12.288 tr(CK) tf(CK) I2S clock rise and fall time Capacitive load CL = 30 pF -8 ns tw(CKH) I2S clock high time Master fPCLK= 36 MHz, audio frequency = 48 kHz 331 - tw(CKL) I2S clock low time 332 - tv(WS) WS valid time Master mode 4 - th(WS) WS hold time Master mode 4 - tsu(WS) WS setup time Slave mode 4 - th(WS) WS hold time Slave mode 0 - Duty Cycle I2S slave input clock duty cycle Slave mode 30 70 % tsu(SD_MR) Data input setup time Master receiver 9 - ns tsu(SD_SR) Data input setup time Slave receiver 2 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 0 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) -29 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 12 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) -3 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2- |
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