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STM32F303VC 数据表(PDF) 105 Page - STMicroelectronics |
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STM32F303VC 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 148 page  tS(1) Sampling time fADC = 72 MHz 0.021 - 8.35 µs - 1.5 - 601.5 1/fADC TADCVREG_STUP(1) ADC Voltage Regulator Start-up time - - - 10 µs tCONV(1) Total conversion time (including sampling time) fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 µs Resolution = 12 bits 14 to 614 (tS for sampling + 12.5 for successive approximation) 1/fADC CMIR(1) Common Mode Input signal Range ADC differential mode (VSSA+VREF+)/2 -10% (VSSA+VREF+)/2 (VSSA+VREF+)/2 + 10% V 1. Data guaranteed by design. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. Table 68. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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