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STS1TX 数据表(PDF) 62 Page - STMicroelectronics

部件名 STS1TX
功能描述  Industrial monitoring and control
PDF  70 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STS1TX 数据表(HTML) 62 Page - STMicroelectronics

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Register table
STS1TX
62/70
DocID025109 Rev 1
PCKTLEN1
0x34
7:0
PCKTLEN1
0
R/W
Length of packet in bytes
(MSB)
PCKTLEN0
0x35
7:0
PCKTLEN0
0x14
R/W
Length of packet in bytes
(LSB)
SYNC4
0x36
7:0
SYNC4
0x88
R/W Sync word 4
SYNC3
0x37
7:0
SYNC3
0x88
R/W Sync word 3
SYNC2
0x38
7:0
SYNC2
0x88
R/W Sync word 2
SYNC1
0x39
7:0
SYNC1
0x88
R/W Sync word 1
MBUS_PRMBL
0x3B
7:0
MBUS_PRMBL[7:0]
0x20
R/W
MBUS preamble length in
chip sequence ‘01’
MBUS_PSTMBL
0x3C
7:0
MBUS_PSTMBL[7:0]
0x20
R/W
MBUS postamble length in
chip sequence ‘01’
MBUS_CTRL
0x3D
7:4
Reserved
00000
R/W
3:1
MBUS_SUBMODE[2:0
]
000
MBUS sub mode: allowed
values are 0, 1, 3 and 5
WM-BUS sub mode:
0: S1 S2 long header,
1: S1m S2 T2 other to meter,
3: T1 T2 meter to other,
5: R2 short header
0Reserved
0
FIFO_CONFIG[1]
0x40
7
Reserved
0
R/W
6:0
TXAFTHR [6:0]
110000
R/W
FIFO almost full threshold for
TX FIFO
FIFO_CONFIG[0]
0x41
7
Reserved
0
R/W
6:0
TXAETHR [6:0]
110000
R/W
FIFO almost empty threshold
for TX FIFO
PCKT_FLT_GOALS[3]
0x4B
7:0
TX_DEST_ADDR
0
R/W TX packet destination fields
PCKT_FLT_GOALS[0]
0x4E
7:0
TX_SOURCE_ADDR
0
R/W TX packet source
PROTOCOL[2]
0x50
23:2
1
Reserved
0
R/W
1: CS value contributes to
timeout disabling
20:1
9
TX_SEQ_NUM_RELO
AD[1:0]
0
TX sequence number to be
used when counting reset is
required using the related
command.
18
RCO_CALIBRATION
0
1: enable the automatic RCO
calibration
17
VCO_CALIBRATION
1
1: enable the automatic VCO
calibration
16
LDC_MODE
0
1: LDC mode on
Table 37. Packet/protocol configuration registers (continued)
Register name
Address
Bit
Field Name
Reset
R/W
Description



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