STS1TX datasheet(23/70 Pages) STMICROELECTRONICS

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STS1TX

Operating modes

those states, at most for any time-out timer duration. Also the READY and LOCK states

behave as transients when they are not directly accessed with the specific commands (for

example, when LOCK is temporarily used before reaching the TX state).

Note:

Response time SHUTDOWN to READY is ~650 µs.

READY state is the default state after the power-on reset event. In the steady condition, the

XO is settled and usable as the time reference for RCO calibration, for frequency synthesis,

and as the system clock for the digital circuits.

The TX mode can be activated directly by the MCU using the TX command, or automatically

if the state machine wakes up from SLEEP mode and some previous TX is pending. The

values are intend to a VCO manual calibration.

In LOCK state the synthesizer is in a locking condition(a). If LOCK state is reached using

specific command LOCKTX, the state machine remains in LOCK state and waits for the

next command. This feature can be used by the MCU to perform preliminary calibrations, as

the MCU can read the calibration word in the RCO_VCO_CALIBR_OUT register and store it

in a non-volatile memory, and after that it requires a further tuning cycle.

When TX is activated by the TX command, the state machine goes into TX state and

remains there until the current packet is fully transmitted or, in the case of direct mode TX,

TXFIFO underflow condition is reached or the SABORT command is applied.

Table 18. States

STATE[6:0](1)

State/mode

Digital LDO

SPI

Xtal

Synth.

Wakeup

timer

Response time

to(2)

SHUTDOWN

OFF (register

contents lost)

Off

0x40

STANDBY

ON (FIFO and

contents

retained)

Off

125 µs

0x36

SLEEP

Off

125 µs

0x03

READY

(Default)

Off

Don’t care

50 µs

0x0F

LOCK

Don’t care

0x5f

Don’t care

1. All others values of STATE[6:0] are invalid and are an indication of an error condition due to bad registers

configuration and/or hardware issue in the application board hosting STS1TX.

2. These values are crystal dependent. The values are referred to 52 MHz.

a. LOCK state is reached when one of the following events occurs first: lock detector assertion or locking timeout

expiration.

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