STS1TX datasheet(29/70 Pages) STMICROELECTRONICS

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STS1TX

Block description

Depending on the RF frequency and channel spacing, a very high accurate crystal or TCXO

may be required.

The RF synthesizer implements fractional sigma delta architecture to allow fast settling and

narrow channel spacing. It is fully integrated and uses a multi-band VCO to cover the whole

frequency range. All internal calibrations are performed automatically.

The PLL output frequency can be configured by programming the SYNT field of the SYNT3,

SYNT2, SYNT1, and SYNT0 registers and BS field of the SYNT0 register. The user must

configure these registers according to the effective reference frequency in use (24 MHz, 26

MHz, 48 MHz, or 52 MHz). In the latter two cases, the user must enable the frequency

divider by 2 for the digital clock, in order to run the digital macro at a lower frequency. The

configuration bit for the digital clock divider is inside the XO_RCO_TEST register (default

case is divider enabled). In addition, the user can also enable a divider by 2 applied to the

reference clock. The configuration bit for the reference clock divider is inside the

SYNTH_CONFIG[1] register. The user must select a 3-bit word in order to set the charge

pump current according to the LO frequency variations, in order to have a constant loop

bandwidth. This can be done by writing the WCP field of the SYNT3 register, according to

the following table:

110

38.5

111

43.0

Table 24. CP word look-up

Channel frequency

WCP [2:0]

145.1

147.1

000

147.1

149.1

001

149.1

151.1

010

151.1

153.2

011

153.2

155.2

100

155.2

157.2

101

157.2

159.2

110

159.2

161.1

111

161.3

163.5

000

163.5

165.7

001

165.7

168.0

010

168.0

170.3

011

170.3

172.5

100

172.5

174.8

101

174.8

177.0

110

177.0

179.3

111

Table 23. Programmability of trans-conductance at startup (continued)

GM_CONF[2:0]

Gm at startup [mS]

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