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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STS1TX 数据表(PDF) 35 Page - STMicroelectronics |
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STS1TX 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 70 page  DocID025109 Rev 1 35/70 STS1TX Transmission and reception The power ramping is enabled by the PA_RAMP_ENABLE bit. If enabled, the ramp starts from the level defined by the word PA_LEVEL_0 and stops at the level defined by the word PA_LEVEL_x, where x is the value of the 3-bit field PA_LEVEL_MAX_INDEX. So, a maximum of 8 steps can be set up. Figure 7 describes the levels table and shows some examples. Each step is held for a time interval defined by the 2-bit field PA_RAMP_STEP_WIDTH. The step width is expressed in terms of bit period units (Tb/8), maximum value is 3 (which means 4×Tb/8=Tb/2). Therefore the PA ramp may last up to 4 Tb (about 3.3 ms if the bit rate is 1.2 kbit/s). Table 26. PA_level PA_LEVEL_x Comment POUT [dBm] (170MHz) 0 No output power: output stage in high impedance mode and all circuits switched off. - 1 Maximum output power 11 … 30 0 … 42 -6 … 90 Minimum level -34 91-127 Reserved N/A |
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