STS1TX datasheet(41/70 Pages) STMICROELECTRONICS

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STS1TX

Transmission and reception

To further improve error correction performance, a data interleaver is used when

convolutional coding is enabled. Data interleaving/de-interleaving is performed using a 4x4-

bit matrix interleaver.

To fill the entire matrix, at least 2 bytes of data payload are required (16 cells). In the

interleaver matrix, the encoded data bits are written along the rows and the sequence to

send to the modulator is obtained by reading the matrix elements along the columns of the

matrix. Due to the size of the matrix, the overall data transmitted must be an exact integer

multiple of two, to fill the rows and columns of the matrix. If necessary, the framer is able to

add automatically extra bytes at the end of the packet, so the number of bytes is an number.

FEC and interleaving are enabled/disabled together.

To enable FEC/INTERL, the field FEC_EN of PCKTCTRL1 must be set to ‘1’. When

FEC/INTERL is enabled, the number of transmitted bits is roughly doubled, hence the on-air

packet duration in time is roughly doubled as well. The data rate specified in Section 9.3.1

always applies to the on-air transmitted data.

A termination byte is automatically appended to set the encoder to the 0-state at the end of

the packet.

9.4.2

CRC

Error detection is implemented by means of cyclic redundancy check codes.

The length of the checksum is programmable to 8, 16, or 24 bits.

The CRC can be added at the end of the packet by the field CRC_MODE of the register

PCKCTRL1.

The following standard CRC polynomials can be selected:

•

CRC mode = 1, 8 bits: the poly is (0x07) X8+X2+X+1

•

CRC mode = 2, 16 bits: the poly is (0x8005) X16+X15+X2+1

•

CRC mode = 3, 16 bits: the poly is (0x1021) X16+X12+X5+1

•

CRC mode = 4, 24 bits: the poly is (0x864CFB)

X24+X23+X18+X17+X14+X11+X10+X7+X6+X5+X4+X3+X+1

•

CRC is calculated over all fields excluding preamble and SYNC word.

9.4.3

Data whitening

To prevent short repeating sequences (e.g., runs of 0’s or 1’s) that create spectral lines,

which may complicate symbol tracking at the receiver or interfere with other transmissions,

the device implements a data whitening feature. Data whitening can be optionally enabled

by setting the filed WHIT_EN of the PCKTCTRL1 register to '1'. Data whitening is

implemented by a maximum length LFSR generating a pseudo-random binary sequence

used to XOR data before entering the encoding chain. The length of the LSFR is set to 9

bits. The pseudo-random sequence is initialized to all 1's.

Data whitening, if enabled, is applied on all fields excluding the preamble and the SYNC

words.

Whitening is applied according to the following LFSR implementation:

STS1TX 数据表(PDF) 41 Page - STMicroelectronics

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