STS1TX datasheet(50/70 Pages) STMICROELECTRONICS

50 / 70 page

MCU interface

STS1TX

50/70

DocID025109 Rev 1

Read and write operations are persistently executed while CSn is kept active (low), the

address being automatically incremented (burst mode).

Accessing the FIFO is done as usual with the read and write commands, by putting, as the

address, the code 0xFF. Burst mode is available to access the sequence of bytes in the

FIFO. Clearly, TX-FIFO with a write operation.

Details of the SPI parameters are reported below.

10.2

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on

a selectable GPIO. The following events trigger an interrupt to the MCU:

Table 28. SPI interface timing requirements

Symbol

Parameter

Min.

Max.

Unit

fSCLK

SCLK frequency

MHz

tsp

CSn low to positive edge on SCLK

µs

Table 29. Interrupts

Bit

Events group

Interrupt event

Packet oriented

Not used

2TX data sent

Not used

TX FIFO underflow/overflow error

Not used

TX FIFO almost full

TX FIFO almost empty

Not used

Signal quality related

Not used

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