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TNETV1647GSTZWT 数据表(PDF) 152 Page - Texas Instruments |
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TNETV1647GSTZWT 数据表(HTML) 152 Page - Texas Instruments |
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152 / 236 page  t2CYC tDH tDS tDH tDS tDH DSTROBE (IORDY) DD[15:0] tCYC(A) tCYC(A) DMARQ at Device tRP DSTROBE (IORDY) at Device STOP (DIOW) at Host HDMARDY (DIOR) at Host DD[15:0] at Device DMACK at Host tRFS DMARQ tMLI DSTROBE (IORDY) STOP (DIOW) HDMARDY (DIOR) DD[15:0] DMACK DA[2:0], ATA_CS0, ATA_CS1 tACK tACK tIORDYZ tCVH tCVS CRC tACK tZAH tAZ tLI tLI tLI tSS TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com A. While DSTROBE (IORDY) timing is tCYC at the device, it may be different at the host due to propagation delay differences on the cable. Figure 6-29. ATA/CF Sustained Ultra DMA Data-In Data Transfer Timing Figure 6-30. ATA/CF Host Pausing an Ultra DMA Data-In Burst Timing Figure 6-31. ATA/CF Device Terminating an Ultra DMA Data-In Burst Timing 152 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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