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TNETV1647GSTZWT 数据表(PDF) 64 Page - Texas Instruments |
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TNETV1647GSTZWT 数据表(HTML) 64 Page - Texas Instruments |
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64 / 236 page  TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 3.2.1 Power Configurations at Reset As described in Section 6.3.1.3, DM6441 Power and Clock Domains, the DM6441 has two power domains: Always On and DSP. There is a shorting switch between the two power domains that must be opened when the DSP domain is powered off and closed when the DSP domain is powered on. The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain. Setting the DSPPWRON bit to a value of 1 closes (enables) the switch and enables the DSP power domain. The default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected (DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of 1. For ARM boot operation (DSP_BT=0), DSPPWRON will be set to the disable value of 0 and must be set by the ARM before the DSP domain power is turned on. Figure 3-1. CHP_SHRTSW Register 31 1 0 RESERVED DSPPWRON R-0000 0000 0000 0000 0000 0000 0000 000 R/W-L LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising Table 3-2. CHP_SHRTSW Register Field Descriptions Bit Field Value Description 31 - 1 RESERVED Reserved 0 DSPPWRON DSP power domain enable 0 Shorting switch open 1 Shorting switch closed 3.2.2 Power Configurations after Reset The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO, Memory Stick/Memory Stick PRO, and GPIOV33. The 3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and described in Table 3-3. By default, these pins are all disabled at reset. Figure 3-2. VDD3P3V_PWDN Register 31 2 1 0 RESERVED IOPWDN1 IOPWDN0 R-0000 0000 0000 0000 0000 0000 0000 00 R/W-1 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Table 3-3. VDD3P3V_PWDN Register Field Descriptions Bit Field Value Description 31 - 2 RESERVED Reserved 1 IOPWDN1 Memory Stick/Memory Stick PRO, MMC/SD/SDIO powerdown controls. 0 I/O buffers powered up 1 I/O buffers powered down 0 IOPWDN0 GIOV33 I/O powerdown controls GIOV33[16:0] pins. 0 I/O buffers powered up 1 I/O buffers powered down 64 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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