TNETV1647GSTZWT datasheet(9/236 Pages) TI1

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TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

TMS320DM6441 Revision History (continued)

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 6.12

•

Added "SDIO is only supported for WLAN operation through TI third parties ..." paragraph

MMC/SD/SDIO

Section 6.12.1

Table 6-43, MMC/SD/SDIO Register Descriptions:

MMC/SD/SDIO

•

Updated/changed 0x01E1 0064 from "SDIO" to "SDIOCTL (SDIO Control Register)"

Peripheral

•

Updated/changed 0x01E1 0068 from "SDIO" to "SDIOST0 (SDIO Status Register 0)"

Description(s)

•

Updated/changed 0x01E1 006C from "SDIO" to "SDIOIEN (SDIO Interrupt Enable Register)"

•

Updated/changed 0x01E1 0070 from "Reserved" to "SDIOIST (SDIO Interrupt Status Register)"

Section 6.13.1.6

Table 6-53, Timing Requirements for VPFE PCLK Master/Slave Mode:

VPFE Electrical

•

Parameter 1 [tc(PCLK)]: Removed MAX value of 160 ns [Cleared Documentation Feedback Issue]

Data/Timing

Section 6.13.2.3

Table 6-63, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

VPBE Electrical

Data Output With Respect to VCLK:

Data/Timing

•

Updated/changed PARAMETER NO. 22 to "Delay time, VCLKIN low to VCLK low" [Cleared

Documentation Feedback Issue]

Section 6.13.2.4

•

Updated/changed "The DM6441's analog video DAC outputs are designed to drive ..." paragraph

DAC Electrical

Data/Timing

Section 6.14.3

Table 6-68, Switching Characteristics Over Recommended Operating Conditions for USB2.0:

USB2.0 Electrical

•

Parameter 5 [tjr(source)NT], HIGH SPEED 480 Mbps:

Data/Timing

–

MAX column: Added footnote reference

Section 6.25.1

Table 6-116, Timing Requirements for Host-Port Interface Cycles:

Host-Port Interface

•

Updated/changed the P = 1/CPU clock frequency in ... footnote from "P = 1.48" to "P = 2.47" ns

(HPI) Electrical

[Cleared Documentation Feedback Issue]

Data/Timing

Section 6.26

•

Removed "TRST is synchronous and must be clocked by TCK ..." NOTE

IEEE 1149.1 JTAG

•

Added Note about the sequencing of all the JTAG signals [Cleared Documentation Feedback Issue]

Section 6.26.1

•

Updated/changed "The JTAG ID register is a read-only register ..." paragraph

JTAG Peripheral

Figure 6-83, JTAG ID Register Description - DM6441 Register Value - 0xXB70 002F:

– JTAG ID Register

•

Updated/changed footnote

Table 6-119, JTAG ID Register Selection Bit Descriptions:

•

Updated/changed DESCRIPTION of Bits 31:28 (VARIANT)

Contents

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