TNETV1647GSTZWT datasheet(12/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

2.3.1

ARM926EJ-S RISC CPU

The ARM subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of

ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications

where full memory management, high performance, low die size, and low power are all important. The

ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to

trade off between high performance and high code density. Specifically, the ARM926EJ-S processor

supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,

providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code

overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

•

ARM926EJ -S integer core

•

CP15 system control coprocessor

•

Memory management unit (MMU)

•

Separate instruction and data caches

•

Write buffer

•

Separate instruction and data tightly-coupled memories (TCMs) [internal RAM] interfaces

•

Separate instruction and data AHB bus interfaces

•

Embedded trace module and embedded trace buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com.

2.3.2

CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and

data caches, tightly-coupled memories (TCMs), memory management unit (MMU), and other ARM

subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,

when the ARM in a privileged mode such as supervisor or system mode.

2.3.3

MMU

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux™,

WindowCE®, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used

to control the address translation, permission checks and memory region attributes for both data and

instruction accesses. The MMU uses a single unified translation lookaside buffer (TLB) to cache the

information held in the page tables. The MMU features are:

•

Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

•

Mapping sizes are:

–

1MB (sections)

–

64KB (large pages)

–

4KB (small pages)

–

1KB (tiny pages)

•

Access permissions for large pages and small pages can be specified separately for each quarter of

the page (subpage permissions)

•

Hardware page table walks

•

Invalidate entire TLB, using CP15 register 8

•

Invalidate TLB entry, selected by MVA, using CP15 register 8

•

Lockdown of TLB entries, using CP15 register 10

Device Overview

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