TNETV1647GSTZWT datasheet(67/236 Pages) TI1

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TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

For further details on the ROM bootloader, see the TMS320DM644x DMSoC ARM Subsystem Reference

Guide (literature number SPRUE14).

3.3.3

DSP Boot

For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be

the master of C64x+ and control booting (host-boot mode). If DSP_BT is high, the C64x+ will boot itself

coming out of device reset (self-boot mode). Table 3-7 shows a summary of the DSP boot modes.

Table 3-7. DSP Boot Modes

DSP_BT

DSP

ARM

DSPBOOTADDR

Brief Description

Boot Mode

Host boot

Internal boot

Programmable

ARM sets an internal DSP memory location in DSPBOOTADDR

internal DSP memory through DMA prior to releasing DSP reset.

Host boot

External boot

Programmable

ARM sets an external DSP memory location in DSPBOOTADDR

releasing DSP reset.

Self boot

Any, except HPI

0x4220 0000

Default EMIFA base address

Host boot

HPI

Programmable

ARM sets a DSP memory location in the DSPBOOTADDR

HPI loads code into the DM6441 memory map with the entry point

set to the memory location specified in the DSPBOOTADDR

should release the DSP from reset.

3.3.3.1

Host-Boot Mode

In host boot mode, the ARM is the master and controls the reset and boot of the C64x+. The C64x+ DSP

remains powered-off after device reset. The ARM is responsible for enabling power to the C64x+ and

releasing it from reset (PSC MMR bits: MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Prior to releasing

the C64x+ reset, the ARM must program the address from which the C64x+ will begin execution in the

DSPBOOTADDR register.

3.3.3.2

Self-Boot Mode

In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset

without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000)

contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache

enabled.

Device Configurations

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