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TNETV1647GSTZWT 数据表(PDF) 84 Page - Texas Instruments |
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TNETV1647GSTZWT 数据表(HTML) 84 Page - Texas Instruments |
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84 / 236 page  TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 3.5.6.9 UART, VPFE, ATA, and GPIO Pin Multiplexing Each UART has independent pin multiplexing control bits in the PINMUX1 register. The UART2 peripheral may be used with or without the flow control signals. Table 3-30 shows how UART2 selection reduces the width of the VPFE interface. Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However, ATA PIO mode is still supported with UART1 enabled. This is shown in Table 3-31. If the ATA module is not enabled, the pins are always configured for use by UART1. Table 3-30. UART2, VPFE, and GPIO Pin Multiplexing PINMUX1 REGISTER MULTIPLEXED PINS BIT FIELDS CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/ UART2 U2FLO CI[7]/ CI[6]/ CI[5]/ CI[4]/ UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/ 0 - CI[7](1) CI[6](1) CI[5](1) CI[4](1) UART_RXD2 UART_TXD2 CCD[13]/ CCD[12]/ 1 0 CI[5](1) CI[4](1) 1 1 UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 (1) Functionality set by VPFE operating mode. Table 3-31. UART1 and ATA Pin Multiplexing PINMUX0 AND PINMUX1 MULTIPLEXED PINS REGISTER BIT FIELDS UART_TXD1/ UART_RXD1/ ATAEN UART1 DMACK DMARQ 0 - UART_TXD1 UART_RXD1 1 0 DMACK DMARQ 1 1 UART_TXD1 UART_RXD1 As Table 3-32 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO. Table 3-32. UART0 and GPIO Pin Multiplexing PINMUX1 REGISTER BIT MULTIPLEXED PINS FIELD UART_TXD0/ UART_RXD0/ UART0 GPIO[36] GPIO[35] 0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0 84 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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