TNETV1647GSTZWT datasheet(31/236 Pages) TI1

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TMS320DM6441

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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

EMIFA FUNCTIONAL PINS: ASYNC / NOR

This pin is multiplexed between EMIFA and HPI.

EM_CS2/

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

I/O/Z

DVDD18

HCS

memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot

and ROM boot modes.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous

EM_CS3

I/O/Z

DVDD18

memories (i.e., NOR flash) or NAND flash.

EM_CS4/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO9/

I/O/Z

DVDD18

For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories

VLYNQ_SCRUN

(i.e., NOR flash) or NAND flash.

EM_CS5/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO8/

I/O/Z

DVDD18

For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories

VLYNQ_CLOCK

(i.e., NOR flash) or NAND flash.

EM_R/W/

This pin is multiplexed between EMIFA, ATA/CF, and HPI.

INTRQ/

I/O/Z

DVDD18

For EMIFA, it is read/write output EM_R/W.

HR/W

EM_WAIT/

(RDY/BSY)/

IPU

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

I/O/Z

IORDY/

DVDD18

For EMIFA, it is wait state extension input EM_WAIT.

HRDY

EM_OE/

(RE)/

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

(IORD)/

I/O/Z

DVDD18

For EMIFA, it is output enable output EM_OE.

DIOR/

HDS1

EM_WE

(WE)

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

(IOWR)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.

DIOW/

HDS2

This pin is multiplexed between EMIFA, ATA/CF, and HPI.

For EMIFA, this is the Bank Address 0 output (EM_BA[0]).

EM_BA[0]/

IPD

When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of

DA0/

I/O/Z

DVDD18

the byte address.

HINT

When connected to a 16-bit asynchronous memory, this pin has the same function

as EMIF address pin 22 (EM_A[22]).

This pin is multiplexed between EMIFA, ATA/CF, and GPIO.

For EMIFA, this is the Bank Address 1 output EM_BA[1].

EM_BA[1]/

When connected to a 16 bit asynchronous memory this pin is the lowest order bit of

DA1/

I/O/Z

DVDD18

the 16-bit word address.

GPIO52

When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the

address.

EM_A[21]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO10/

I/O/Z

DVDD18

For EMIFA, it is address bit 21 output EM_A[21].

VLYNQ_TXD0

EM_A[20]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO11/

I/O/Z

DVDD18

For EMIFA, it is address bit 20 output EM_A[20].

VLYNQ_RXD0

EM_A[19]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO12/

I/O/Z

DVDD18

For EMIFA, it is address bit 19 output EM_A[19].

VLYNQ_TXD1

EM_A[18]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO13/

I/O/Z

DVDD18

For EMIFA, it is address bit 18 output EM_A[18].

VLYNQ_RXD1

EM_A[17]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO14/

I/O/Z

DVDD18

For EMIFA, it is address bit 17 output EM_A[17].

VLYNQ_TXD2

EM_A[16]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO15/

I/O/Z

DVDD18

For EMIFA, it is address bit 16 output EM_A[16].

VLYNQ_RXD2

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