 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TNETV1647GSTZWT 数据表(PDF) 89 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV1647GSTZWT 数据表(HTML) 89 Page - Texas Instruments |
|
|
89 / 236 page  SCR5 SCR1 Bridge2 CF/ATA VLYNQ EMAC USB2.0 SCR2 Bridge1 Bridge7 ARM C64x+ L2Cache VICP Bridge6 Bridge5 SCR3 VPSS EDMA3TC1 Bridge3 ARM TCM C64x+ L2/L1 DDR2Ctrl (Mem/Reg) SCR6 CF/ATA Reg USBReg EMACReg EMACCtrlModReg EMACCtrlModRAM MDIO VPSSReg SPI0/1 GPIO AINTC SystemReg PSC PLLC0 PLLC1 Bridge9 Bridge8 SCR7 ASP VLYNQ MMC/SD EMIFA/NAND SCR8 UART0 UART1 UART2 I2C PWM0 PWM1 PWM2 Timer0 Timer1 Timer2 SCR4 EDMA3CC EDMA3TC0 EDMA3TC1 32 32 32 32 64 32 32 32 32 64 64 64 64 64 Read Write Read Write 64 64 64 64 64 128 256 32 32 32 32 32 32 64 64 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 DSP/2ClockRate DSP/3ClockRate DSP/6ClockRate EDMA3TC0 MXI/CLKINRate 32 32 HPI 32 HPI 32 MS/MSPRO 32 32 32 32 32 32 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 4.1 System Interconnect Block Diagram Figure 4-1 displays the DM6441 system interconnect block diagram. The following is a list that helps interpret this diagram: • The direction of the arrows indicates either bus master or bus slave. • The arrow originates at a bus master and terminates at a bus slave. • The direction of the arrows does not indicate the direction of data flow. Data flow is typically bi-directional for each of the documented bus paths. • The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3, or DSP/6 clock rate. • Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple instances shown for a variety of reasons, some of which are described below: – The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register access, data access, and/or memory access. Examples of these peripherals are C64x+ megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI. – The peripheral/module has a master port as well as slave memories. Examples of these are the C64x+ megamodule and the ARM subsystem. Figure 4-1. System Interconnect Block Diagram Copyright © 2006–2010, Texas Instruments Incorporated System Interconnect 89 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
