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TNETV1647GSTZWT 数据表(PDF) 72 Page - Texas Instruments |
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TNETV1647GSTZWT 数据表(HTML) 72 Page - Texas Instruments |
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72 / 236 page  TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 3.5 Configurations After Reset The following sections give the details on configuring the device after reset. 3.5.1 Switched Central Resource (SCR) Bus Priorities Prioritization within the switched central resource (SCR) is programmable for each master. The register bit fields and default priority levels for DM6441 bus masters are shown in Table 3-12. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and Figure 3-6. The C64x+, VPSS, and EDMA3 masters contain registers that control their own priority values. Table 3-12. DM6441 Default Bus Master Priorities Priority Bit Field Bus Master Default Priority Level VPSSP VPSS 0 (VPSS PCR registerRegister, DMA_PRI bit field) [For more detailed information on the DMA_PRI bit field, see the TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (literature number SPRUE37).] EDMATC0P EDMATC0 0 (EDMA3CC QUEPRI register) [For more detailed information on the QUEPRI register, see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).] EDMATC1P EDMATC1 0 (EDMA3CC QUEPRI register) [For more detailed information on the QUEPRI register, see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).] ARM_DMAP ARM (DMA) 1 (MSTPRI0 register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 register) C64X+_DMAP C64X+ (DMA) 7 (C64x+ MDMAARBE.PRI register bit field) [For more detailed information on the PRI bit field, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).] C64X+_CFGP C64X+ (CFG) 1 (MSTPRI0 register) EMACP EMAC 4 (MSTPRI1 register) USBP USB 4 (MSTPRI1 register) ATAP ATA/CF 4 (MSTPRI1 register) VLYNQP VLYNQ 4 (MSTPRI1 register) HPIP HPI 4 (MSTPRI1 register) VICPP VICP 5 (MSTPRI0 Register) Figure 3-5. MSTPRI0 Register 31 19 18 16 RESERVED VICPP(1) R-0000 0000 0000 0 R/W-101 15 11 10 8 7 6 4 3 2 0 RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001 LEGEND: R = Read; W = Write; -n = value after reset (1) The VICPP bit field is configured by the third-party software. When modifying the MSTPRI0 register a read/modify/write must be performed to preserve the configuration set by the third-party software. 72 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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