TNETV1647GSTZWT datasheet(96/236 Pages) TI1

96 / 236 page

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

6.3.1.1

Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize

inductance and resistance in the power delivery path. Additionally, when designing for high-performance

applications utilizing the DM6441 device, the PC board should include separate power planes for core,

I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

6.3.1.2

Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to DM6441. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for

the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6441 power pins, no

more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better

because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass

caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can

be obtained in a small package) should be next closest. TI recommends no less than eight small and

eight medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space

and at least the corners of the "exterior".

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order

of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be

placed outside of the BGA footprint.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of

any component, verification of capacitor availability over the product’s production lifetime should be

considered.

6.3.1.3

DM6441 Power and Clock Domains

DM6441 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain

is always on when the chip is on. The "Always On" domain is powered by the VDD pins of the DM6441.

The majority of the DM6441's modules lie within the "Always On" power domain. A separate domain called

the "DSP" domain houses the C64x+ and VICP. The "DSP" domain is not always on. The "DSP" power

domain is powered by the CVDDDSP pins of the DM6441. Table 6-3 provides a listing of the DM6441 power

and clock domains.

Two primary reference clocks are required for the DM6441 device. These can either be crystal input or

driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the

internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3.

The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals

at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For

further description of the DM6441 clock domains, see Table 6-4 (DM6441 Clock Domains) and Figure 6-6

(PLL1 and PLL2 Clock Domain Block Diagram).

Peripheral and Electrical Specifications

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