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TNETV1647GSTZWT 数据表(PDF) 79 Page - Texas Instruments |
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TNETV1647GSTZWT 数据表(HTML) 79 Page - Texas Instruments |
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79 / 236 page  TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6.2 VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing The CCD and LCD controllers in the VPSS require multiplex control bit settings for certain modes of operation. Bits within the PinMux0 register, which select between the CCD or LCD control signal function and GPIO, are summarized in Table 3-18. Table 3-18. VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing PINMUX0 REGISTER FIELDS MULTIPLEXED PINS C_FIELD/ LCD_FIELD/ C_WE/ LCD_OE/ CFLDEN LFLDEN CWE LOEEN R0/ B0/ GPIO[1] GPIO[0] GPIO[4] GPIO[3] - - - 0 - - - GPIO[0] - - - 1 - - - LCD_OE - - 0 - - - GPIO[1] - - - 1 - - - C_WE - - 0 - - - B0/GPIO[3](1) - - - 1 - - - LCD_FIELD - - 0 - - - R0/GPIO[4](1) - - - 1 - - - C_FIELD - - - (1) Depends on RGB888 bit setting, see Table 3-19. 3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19 and Table 3-20. Enabling PWM2, PWM1, CCD, and LCD functionality overrides the RGB modes. RGB666 interface pin functionality requires setting the RGB666 PINMUX0 register bit field to ‘1’ and PINMUX1 register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0 register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, CFLDEN, and LFLDEN must be set to ‘0’. Table 3-19. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS PWM2/ PWM1/ C_FIELD/ LCD_FIELD/ RGB888 RGB666 PWM2 PWM1 CFLDEN LFLDEN B2/ R2/ R0/ B0/ GPIO[47] GPIO[46] GPIO[4] GPIO[3] 0 0 0 0 0 0 GPIO[47] GPIO[46] GPIO[4] GPIO[3] - - - - - 1 - - - LCD_FIELD - - - - 1 - - - C_FIELD - - - - 1 - - - PWM1 - - - - 1 - - - PWM2 - - - 0 1 0 0 0 0 B2 R2 GPIO[4] GPIO[3] 1 - 0 0 0 0 B2 R2 R0 B0 Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS R1/ B1/ G1/ G0/ RGB888 PWM2 PWM1 CFLDEN LFLDEN GPIO[38] GPIO[6] GPIO[5] GPIO[2] 0 0 0 0 0 GPIO[38] GPIO[6] GPIO[5] GPIO[2] 1 0 0 0 0 R1 B1 G1 G0 Copyright © 2006–2010, Texas Instruments Incorporated Device Configurations 79 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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