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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS2 数据表(PDF) 52 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Power saving modes ST7LITEUS2, ST7LITEUS5 52/136 Figure 22. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-halt mode by means of a reset. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 8.4.2 Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when Active-halt mode is disabled. The MCU can exit Halt mode on reception of either a specific interrupt (see Table 9: Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see Section 14.1: Option bytes for more details). HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) IBIT ON OFF 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS 2) IBIT ON OFF X 4) ON CPU OSCILLATOR PERIPHERALS IBITS ON ON X 4) ON 64 CPU CLOCK CYCLE DELAY (Active-halt enabled) Obsolete Product(s) - Obsolete Product(s) |
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