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ST7LITEUS2 数据表(PDF) 83 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 83/136 ADC data register high (ADCDRH) Reset value: 0000 0000 (00h) ADC control/data register Low (ADCDRL) Reset value: 0000 0000 (00h) 7 0 D9 D8 D7 D6 D5 D4 D3 D2 Read only Bits 7:0 D[9:2] MSB of Analog Converted value 7 0 0000 SLOW 0 D1 D0 Read/write Bits 7:4 Reserved. Forced by hardware to 0. Bit 3 SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below (see Table 33: Configuring the ADC clock speed). Bit 2 Reserved. Forced by hardware to 0. Bits 1:0 D[1:0] LSB of Analog Converted value Table 33. Configuring the ADC clock speed fADC SLOW SPEED fCPU/2 0 0 fCPU 01 fCPU/4 1 x Table 34. ADC register map and reset values Address (Hex.) Register label 76 543 21 0 0034h ADCCSR Reset value EOC 0 SPEED 0 ADON 0 0 0 0 0 CH2 0 CH1 0 CH0 0 0035h ADCDRH Reset value D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 0036h ADCDRL Reset value 0 0 0 0 0 0 0 0 SLOW 0 0 0 D1 0 D0 0 Obsolete Product(s) - Obsolete Product(s) |
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