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ST7LITEUS2 数据表(PDF) 42 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Interrupts ST7LITEUS2, ST7LITEUS5 42/136 Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function. 7.3.2 External Interrupt Control register 2 (EICR2) Reset value: 0000 0000 (00h) Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function. 3 IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes. 7 0 0 0 0 0 IS41 IS40 IS31 IS30 Read/Write Bits 7:4 Reserved Bits 3:2 IS4[1:0] ei4 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 10. Bits 1:0 IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 10. Table 10. Interrupt sensitivity bits ISx1 ISx0 External interrupt sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge Obsolete Product(s) - Obsolete Product(s) |
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