ST7LITEUS2 datasheet(32/136 Pages) STMICROELECTRONICS

32 / 136 page

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Supply, reset and clock management

ST7LITEUS2, ST7LITEUS5

32/136

6.3.4

AVD Threshold Selection register (AVDTHCR)

Reset value: 0000 0011 (03h)

6.3.5

Clock Controller Control/Status register (CKCNTCSR)

Read/Write

Reset value: 0000 1001 (09h)

CK2

CK1

CK0

AVD1

AVD0

Read / Write

Bits 7:5 CK[2:0] Internal RC Prescaler Selection

These bits are set by software and cleared by hardware after a reset. These bits

select the prescaler of the internal RC oscillator. See Figure 10 on page 34 and

Table 6.

Bits 4:2 Reserved, must be kept cleared.

Bits 1:0 AVD Threshold Selection bits. Refer to Section 7.4: System integrity management

(SI).

Table 6.

Internal RC prescaler selection bits(1)

If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be

enabled in the RC prescaler.

CK2

CK1

CK0

fOSC

fRC

fRC/2

fRC/4

fRC/8

fRC/16

0000

AWU_FLAG

RC_

FLAG

0RC/AWU

Read / Write

Bits 7:4 Reserved, must be kept cleared.

Bit 3 AWU_FLAG AWU Selection

This bit is set and cleared by hardware

0: No switch from AWU to RC requested

1: AWU clock activated and temporization completed

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