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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS2 数据表(PDF) 69 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 69/136 10.1.6 Register description Lite timer control/status register (LTCSR) Reset value: 0000 0x00 (0xh) 7 0 ICIE ICF TB TBIE TBF WDGR WDGE WDGD Read / Write Bit 7 ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register Bit 5 TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz) Bit 4 TBIE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled 1: Timebase (TB) interrupt enabled Bit 3 TBF Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred Obsolete Product(s) - Obsolete Product(s) |
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