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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS2 数据表(PDF) 37 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management 37/136 6.4.5 Internal watchdog reset The reset sequence generated by a internal watchdog counter overflow is shown in Figure 13. Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 13. Reset sequences 6.5 Register description 6.5.1 Multiplexed I/O Reset Control register 1 (MUXCR1) Reset value: 0000 0000 (00h) 6.5.2 Multiplexed I/O Reset Control register 0 (MUXCR0) Reset value: 0000 0000 (00h) VDD Run RESET PIN EXTERNAL WATCHDOG ACTIVE PHASE VIT+(LVD) VIT-(LVD) th(RSTL)in Run WATCHDOG UNDERFLOW tw(RSTL)out Run Run RESET RESET SOURCE EXTERNAL RESET LVD RESET WATCHDOG RESET INTERNAL RESET (64 TCPU) VECTOR FETCH ACTIVE PHASE ACTIVE PHASE 7 0 MIR15 MIR14 MIR13 MIR12 MIR11 MIR10 MIR9 MIR8 Read / Write once 7 0 MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0 Read / Write once Bits 15:0 MIR[15:0] Obsolete Product(s) - Obsolete Product(s) |
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