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ST7LITEUS2 数据表(PDF) 51 Page - STMicroelectronics

部件名 ST7LITEUS2
功能描述  Interrupt management
PDF  136 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITEUS2 数据表(HTML) 51 Page - STMicroelectronics

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Obsolete
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ST7LITEUS2, ST7LITEUS5
Power saving modes
51/136
8.4.1
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a
reset.
When exiting Active-halt mode by means of a reset, a 64 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation by fetching the reset vector which woke
it up (see Figure 22).
When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see Figure 22).
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 21.
Active-halt timing overview
halt
Run
Run
64 CPU
CYCLE DELAY 1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
Active
[Active-halt Enabled]
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Product(s)
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Product(s)



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