ST7LITEUS2 datasheet(25/136 Pages) STMICROELECTRONICS

25 / 136 page

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ST7LITEUS2, ST7LITEUS5

Central processing unit

25/136

Bit 7:5 Set to ‘1’

Bit 4 H Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU

during an ADD or ADC instruction. It is reset by hardware during the same

instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD

arithmetic subroutines.

Bit 3 I Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all

interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the

JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I

is cleared. By default an interrupt routine is not interruptible because the I bit

is set by hardware at the start of the routine and reset by the IRET

instruction at the end of the routine. If the I bit is cleared by software in the

interrupt routine, pending interrupts are serviced regardless of the priority

level of the current interrupt routine.

Bit 2 N Negative

This bit is set and cleared by hardware. It is representative of the result sign of the

last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 Z Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last

arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an

underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and

JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate

instructions.

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ST7LITEUS2 数据表(PDF) 25 Page - STMicroelectronics

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