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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS2 数据表(PDF) 30 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Supply, reset and clock management ST7LITEUS2, ST7LITEUS5 30/136 Figure 9. Clock switching 6.3 Register description 6.3.1 Main Clock Control/Status register (MCCSR) Reset value: 0000 0000 (00h) Internal RC AWU RC Set RC/AWU Poll AWU_FLAG until set Internal RC Reset RC/AWU Poll RC_FLAG until set AWU RC 7 0 000 000 MCO SMS Read / Write Bits 7:2 Reserved, must be kept cleared. Bit 1 MCO Main Clock Out enable bit This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC ) 1: Slow mode (fCPU = fOSC/32) Obsolete Product(s) - Obsolete Product(s) |
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