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ST7LITEUS2 数据表(PDF) 114 Page - STMicroelectronics |
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ST7LITEUS2 数据表(HTML) 114 Page - STMicroelectronics |
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114 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST7LITEUS2, ST7LITEUS5 114/136 Refer also to Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions. Figure 61. RESET pin protection when LVD is enabled 1. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull- down capacitor is required to filter noise on the reset line. 2. When using the LVD: - Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 2 and text above) - Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M Ω pull-down on the RESET pin. - The capacitors connected on the RESET pin and also the power supply are key to avoid any startup marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.” 3. In case a capacitive power supply is used, it is recommended to connect a 1M Ω pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU). Table 65. Asynchronous RESET pin characteristics (1) 1. TA = -40°C to 125°C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3VDD V VIH Input high level voltage 0.7VDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis(2) 2. Data based on characterization results, not tested in production. 2V VOL Output low level voltage(3) 3. The IIO current sunk must always respect the absolute maximum rating specified in Table 44 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. VDD=5 V IIO=+2 mA 400 mV RON Pull-up equivalent resistor(4) 4. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD. VIN=VSS VDD=5 V 30 50 70 k Ω VDD=3 V 90(2) tw(RSTL)out Generated reset pulse duration Internal reset sources 90(2) μs th(RSTL)in External reset pulse hold time (5) 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 20 μs tg(RSTL)in Filtered glitch duration 200 ns 0.01 μF ST7XXX PULSE GENERATOR Filter RON VDD INTERNAL RESET RESET EXTERNAL Required 1M Ω Optional (note 3) WATCHDOG LVD RESET ILLEGAL OPCODE 5) Obsolete Product(s) - Obsolete Product(s) |
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