WM8803CDTSLASHV datasheet(40/45 Pages) WOLFSON

40 / 45 page

WM8803

Product Preview

PP Rev 1.1 September 2003

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

CRC

Address

Control

Track

Index

Minute

Second

Frame

Zero

abs minute

abs second

abs frame

Table 24 Output Register: Sub-code Q Data with CRC Flags Output (0xED)

The cyclic redundancy code (CRC) is a set of flags that indicates the correctness of the 80bits of

sub-code Q data. Note that the same data is output for both the DO0 and DO1 CRC flags.

When sub-code Q data is included in the input data, the result of the CRC calculation can be read

out along with the data.

To read out the sub-code Q data, the data must be read out with INTQSY set as the E/INT interrupt

output function, and the IC must be set up to output the load signal.

When sub-code Q data is detected, the E/INT signal will output a high level or a high-level pulse. The

sub-code Q data is updated on each rising edge on the E/INT signal. Applications must complete

readout of this data within 13.3ms (standard speed) or 6.6ms (2 × speed) of the rising edge of the

E/INT signal.

CRC

OUTPUT CONDITIONS

Errors were found in the sub-code Q data.

The sub-code Q data is correct.

Table 25 CRC Flag Output

WM8803CDT/V 数据表(PDF) 40 Page - Wolfson Microelectronics plc

WM8803CDT/V 数据表(HTML) 40 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载