WM8803CDTSLASHV datasheet(22/45 Pages) WOLFSON

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WM8803

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PP Rev 1.1 September 2003

When XIN is set to be the clock source with OCKSEL, the PLL circuit will operate as long as PLL

operation is not stopped by PDOWN[1:0] or PLLOPR. In this mode the state of the PLL circuit is

always output from the ERROR pin. Regardless of the PLL state information processed can be read

out over the micro-controller interface.

ERROR

SDATAO

PLL locked state

SDIN data

Muted

Demodulated data

Muted

SDIN data

UGPI

LOCK

UNLOCK

UGPI: When the clock switching transition period signal is selected

Figure 17 SDATO Output Data Switching Timing Chart (when RDTSEL is set to “0”)

INPUT DATA SAMPLING FREQUENCY CALCULATION

This function calculates the input data sampling frequency using the XIN clock.

In modes where the oscillator amplifier is automatically stopped due to PLL circuit lock, the fs

calculation is performed and ERROR indicates the error state. Calculation completes at the same

time the oscillator amplifier is stopped and the fs value is retained. After calculation is confirmed, the

value does not change until the PLL circuit goes to the unlocked state. In continuous operation

mode, the oscillator amplifier continuously repeats the frequency calculation. Even when sampling

the input data during which the channel status sampled information does not change within the PLL

capture range, it will still be possible to read out a calculated result that follows the input data.

The calculated result can be read out from CCB address 0xEC or output registers DO4 to DO6. Note,

however, that when the PLL synchronizes with data that corresponds to 32k to 192kHz. The fs

calculation mode can be selected from two modes; a 32k to 96kHz calculation mode and a 64k to

192kHz calculation mode and is switched by FS4XIN. It is not possible to monitor an fs calculation

result for the whole 32k to 192kHz range at the same time.

In systems that connect CLKOUT to XIN and thus do not require an oscillator element, the fs

calculation result will always be “out of range”.

ERROR OUTPUT AND PROCESSING (ERROR)

LOCK ERROR AND DATA ERROR OUTPUT

The ERROR pin outputs a high level when the PLL is in the unlocked state or an error occurs in the

transmitted data.

PLL LOCK ERROR

The PLL circuit will go to the unlocked state for input data that does not conform to the bi-phase

modulation rules and for input data in which the preamble B, M, and W cannot be detected.

The ERROR output goes to the high level when a PLL lock error occurs and is held high until data

modulation has returned to normal for 15 to 50ms.

The rise and fall of the ERROR output is synchronized with LRCLK.

INPUT DATA TRANSMISSION ERROR

Odd input parity errors are detected from the parity bits in the input data.

When input parity errors occur for 9 or more consecutive cycles, the ERROR output goes high. The

high level is held until the PLL is in a locked state for 15 to 50ms, then ERROR returns low.

When 8 or fewer consecutive input parity errors occur, an error will only be output for intervals

between sub-frames for errors that occurred only when non-PCM data is recognized by the channel

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