WM8803CDTSLASHV datasheet(13/45 Pages) WOLFSON

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WM8803

PP Rev 1.1 September 2003

The oscillator amplifier normally stops automatically when the PLL is locked, but continuous

operation can be set by AMPCNT. Setting the WM8803 to continuous operation mode makes it

possible to calculate the input sampling frequency when the PLL is locked. However, since both the

oscillator amplifier clock and the PLL clock signals will be present, users must determined whether or

not this adversely affects audio quality.

The oscillator amplifier can be stopped when not required by setting the AMPOPR. When returning

from stopped mode to operating mode the application must maintain its state for at least 10ms until

the oscillator stabilizes and normal operation resumes.

OUTPUT CLOCKS (CLKOUT, BCLK, LRCLK)

The clock source for the clock outputs CLKOUT, BCLK, and LRCLK can be selected from two

master clocks: the PLL circuit and the XIN pin.

Normally, when the PLL circuit is locked master clock is switched to the PLL source. When the PLL

circuit is unlocked, master clock automatically switches to the XIN source. The clock source can be

forcibly selected by setting OCKSEL. Clock continuity is maintained when the clock source is

switched due to the locked/unlocked state of the PLL circuit or by setting OCKSEL.

Clock switching depends on the PLL circuit locked/unlocked state at the time OCKSEL is set. If the

PLL source is selected by OCKSEL when the PLL circuit is unlocked, the switch will occur

automatically after the PLL circuit locks.

When VCO operation is stopped by setting PLLOPR, XIN becomes the clock source. However, clock

continuity cannot be maintained if the stopped state is set with the PLLOPR while the PLL circuit is

locked. Continuity cannot be maintained when switching from the PLL locked state with low power

mode set.

OCKSEL

PLL state

Locked

Unlocked

Locked

Unlocked

Clock source

PLL

XIN

Table 5 Command Settings, PLL States, and the Clock Source

Either the PLL clock or the XIN clock is output from CLKOUT. The CLKOUT clock signal is divided to

create the signals output from BCLK and LRCLK.

The frequency when the PLL circuit is locked is set with the PLLCK[1:0]. When switching from the

512fs setting, (PLLCK[1:0] = “10”) to the (512/2)fs setting (PLLCK[1:0] = “11”) in the PLL locked

state, it is possible to maintain clock continuity without losing the PLL lock. This is also true when

changing the frequency is the opposite direction..

Using the procedure shown in Figure 6 to switch between 512fs and (512/2)fs, the BCLK and LRCLK

output clock will maintain continuity and allow the CLKOUT output clock frequency to be held within a

narrow band.

WM8803CDT/V 数据表(PDF) 13 Page - Wolfson Microelectronics plc

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