WM8803CDTSLASHV datasheet(28/45 Pages) WOLFSON

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WM8803

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PP Rev 1.1 September 2003

MICRO-CONTROLLER INTERFACE (E/INT, CE, CL, DI, DO)

INTERRUPT OUTPUT (E/INT)

The E/INT pin can be set to function as the micro-controller interface interrupt output using INTSEL.

An interrupt is issued when a change occurs in the PLL lock state, the output data information or

other aspects of WM8803 operation.

The interrupt output function consists of registers for selecting interrupts, the E/INT pin to output

those state transitions, and the registers that store interrupt related data.

The E/INT pin normally outputs a low level, but outputs a high level when an interrupt occurs. After

outputting a high level, it returns to the low level according to the INTOPF setting.

INTOPF selects whether the E/INT pin holds the high level for a fixed period and then is cleared

(returning to the low level), or is cleared at the same time as the output register is read.

The interrupts can be selected from the items listed in Table 13. More than one of these items can be

set to be interrupts at the same by setting the contents of CCB address 0xEA. The interrupt signal is

issued whenever any one of the interrupt events occurs.

E/INT output = (selected interrupt 1) + (selected interrupt 2) + ... + (selected interrupt n)

NO.

COMMAND

DESCRIPTION

INTERR

Output when the state of the ERROR pin changes.

INTPCM

Output when the state of the AUDIO pin changes.

INTEMP

Output when the state of the pre-emphasis information changes.

INTVFL

Output when the state of the validity flag changes.

INTFSC

Output when the input fs calculation result changes.

INTCSF

Output when the first 48 bits of the channel status data is updated.

INTSQY

Output when the sub-code Q data can be read out.

Table 13 Interrupt Event Settings

When an interrupt event occurs the content of the selected interrupt events is stored in the CCB

address 0xEB output registers DO1 to DO7. The read registers for event items 1 through 4 read out

the current state of those events regardless of the E/INT output. For event items 5 through 7, the

state is stored when the event occurs.

To monitor interrupt event item 5 in the PLL locked state, the oscillator amplifier must be set to

continuous operation mode, since the oscillator amplifier clock is used.

When E/INT is set to output a high-level pulse when interrupt event occurs, the pulse width for each

interrupt event will be between 1/2 fs and 3/2 fs.

When the WM8803 is set so that E/INT is cleared after the output register is read, the clear operation

is performed immediately after output register 0xEB is reset. The data for interrupt events 6 and 7 is

updated within the periods shown in Table 14, the corresponding read registers should be read as

soon as possible after the event is detected.

DATA

UPDATE INTERVAL

Channel status and preamble B

2ms to 6ms

Sub-code Q data

13.3ms (fs = 44.1kHz), 6.65ms (2x speed)

Table 14 Data Update Intervals (Input fs = 32k to 96kHz)

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