WM8803CDTSLASHV datasheet(32/45 Pages) WOLFSON

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WM8803

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PP Rev 1.1 September 2003

WRITE DATA DETAILED DOCUMENTATION

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

MCKHFO

PLLCK1

PLLCK0

PLLOPR

PDOWN1

PDOWN0

SYSRST

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

XISEL3

XISEL2

XISEL1

XISEL0

OCKSEL

AMPCNT

AMPOPR

Table 17 Input Register Function Settings 1: System Settings (0xE8)

SYSRST:

System reset

0: No reset performed (initial value)

1: Reset all circuits other than the command registers.

PDOWN[1:0]:

Low power mode settings

(Allows the operation of specific

functions only)

00: Normal operation (initial value)

01: Only the oscillator amplifier operates.

10: Only the oscillator amplifier and the output clock divider operate.

11: Reserved

PLLOPR:

PLL (VCO) operate/stop setting

0: Operate (initial value)

1: Stop

PLLCK[1:0]:

PLL locked state clock frequency setting

00: 256fs (initial value)

01: 384fs

10: 512fs

11: (512/2)fs = 256fs

MCKHFO:

CLKOUT output clock frequency setting

0: 1/1 output (initial value)

1: 1/2 output

In the PLL locked state when switching from the 512fs setting with the PLLCK[1:0] = “10” to the

(512/2)fs setting with the PLLCK[1:0] = “11” it is possible to maintain clock continuity without entering

the PLL lock error state..This is also the case when switching in the reverse direction.

For systems such as portable equipment power consumption can be minimized,by setting

PLLCK[1:0]

= “00” (256fs). Systems such as AV amplifiers that required best performance, the

PLLCK[1:0]

= “10” (512fs) or the PLLCK[1:0] = “11” (512/2fs) setting is recommended.

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